In a standard cell architecture, oxide definition (OD) (e.g., diffusion) areas are contained within a cell area. That is, the diffusion areas are within the cell and do not extend beyond (or even near) cell edges. Active devices associated with the diffusion areas are also located within the cell boundaries. Typically, devices at edges of a diffusion area show a performance degradation. For example, devices fabricated with a 20 nm process technology may have a thirty percent performance degradation. The degradation may result from a reduced Silicon Germanium (SiGe) deposition at the diffusion edges. The reduced Silicon Germanium results in less stress on a device channel region. Thus, conventional cell layouts have avoided placement of active devices at the diffusion area edges.
Dummy fields of pure oxide (PO) may be at the cell edges. These dummy fields may be referred to as dummy gates. The dummy gates (PO) are not associated with diffusion areas. Because the dummy gates are not associated with diffusion areas, the dummy gates are not part of active devices. Therefore, active devices are not provided on the cell edges.
FIG. 1 illustrates a conventional standard cell architecture 100. The conventional cell 100 includes diffusion areas 102, conductive (e.g., metal) lines 104, a polysilicon gate 106, dummy gates 108, and a cell boundary 110. In the conventional cell 100, the dummy gates 108 are not active devices because they do not overlap with the diffusion areas 102.